Sample Waveforms for pll1.vhd

Sample behavioral waveforms for design file pll1.vhd

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design pll1.vhd. The design pll1.vhd has Cyclone II PLL_TYPE pll configured in SOURCE_SYNCHRONOUS mode The primary clock input to the PLL is INCLK0, with clock period 55555 ps.

Fig. 1 : Wave showing SOURCE_SYNCHRONOUS mode operation.